Design Verification Engineer

Verification Engineer - Cambridge (can do remote within the UK) Senior and Principal Verification Engineers I am seeking highly skilled and detail-oriented Verification Engineers to join a dynamic start-up, who have gone through successful funding rounds, have live projects with well known clients and growing the team week on week! You will be responsible for applying formal methods to verify the correctness of hardware designs, ensuring that the systems meet functional specifications and are free of design errors. This position offers an exciting opportunity to work on cutting-edge technologies and contribute to the development of robust and reliable systems. With projects already in full flow and partnerships with some global names, this is a great opportunity for Juniors and Seniors alike to join! Required Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field. (PLUS) Proven experience with formal verification tools (e.g., Cadence JasperGold, Synopsys VC Formal, or equivalent tools). Hands-on experience with RTL design languages such as Verilog, SystemVerilog, or VHDL. Experience with verification methodologies such as UVM (Universal Verification Methodology) or other simulation-based verification techniques. Experience with assertions (e.g., SVA - SystemVerilog Assertions) and formal verification environments. On offer is the chance to join an early stage start-up with a founder who has already had previous success within the Semiconductor space. You will get equity and a competitive base salary. The role is open to Principal and Senior candidates. You must have UK working rights to be considered for this role. For more information, please contact Rachel Mason at IC Resources.